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k60p100m100sf2 k60 sub-family data sheet supports the following: mk60dn256zvll10, mk60dx256zvll10, mk60dn512zvll10 features ? operating characteristics C voltage range: 1.71 to 3.6 v C flash write voltage range: 1.71 to 3.6 v C temperature range (ambient): -40 to 105c ? performance C up to 100 mhz arm cortex-m4 core with dsp instructions delivering 1.25 dhrystone mips per mhz ? memories and memory interfaces C up to 512 kb program flash memory on non- flexmemory devices C up to 256 kb program flash memory on flexmemory devices C up to 256 kb flexnvm on flexmemory devices C 4 kb flexram on flexmemory devices C up to 128 kb ram C serial programming interface (ezport) C flexbus external bus interface ? clocks C 3 to 32 mhz crystal oscillator C 32 khz crystal oscillator C multi-purpose clock generator ? system peripherals C 10 low-power modes to provide power optimization based on application requirements C memory protection unit with multi-master protection C 16-channel dma controller, supporting up to 64 request sources C external watchdog monitor C software watchdog C low-leakage wakeup unit ? security and integrity modules C hardware crc module to support fast cyclic redundancy checks C hardware random-number generator C hardware encryption supporting des, 3des, aes, md5, sha-1, and sha-256 algorithms C 128-bit unique identification (id) number per chip ? human-machine interface C low-power hardware touch sensor interface (tsi) C general-purpose input/output ? analog modules C two 16-bit sar adcs C programmable gain amplifier (pga) (up to x64) integrated into each adc C 12-bit dac C three analog comparators (cmp) containing a 6-bit dac and programmable reference input C voltage reference ? timers C programmable delay block C eight-channel motor control/general purpose/pwm timer C two 2-channel quadrature decoder/general purpose timers C ieee 1588 timers C periodic interrupt timers C 16-bit low-power timer C carrier modulator transmitter C real-time clock freescale semiconductor document number: k60p100m100sf2 data sheet: advance information rev. 5, 5/2011 this document contains information on a new product. specifications and information herein are subject to change without notice. ? 2010C2011 freescale semiconductor, inc. preliminary
? communication interfaces C ethernet controller with mii and rmii interface to external phy and hardware ieee 1588 capability C usb full-/low-speed on-the-go controller with on-chip transceiver C two controller area network (can) modules C three spi modules C two i2c modules C five uart modules C secure digital host controller (sdhc) C i2s module k60 sub-family data sheet data sheet, rev. 5, 5/2011. 2 preliminary freescale semiconductor, inc.
table of contents 1 ordering parts ...........................................................................5 1.1 determining valid orderable parts......................................5 2 part identification ......................................................................5 2.1 description.........................................................................5 2.2 format ...............................................................................5 2.3 fields .................................................................................5 2.4 example ............................................................................6 3 terminology and guidelines ......................................................6 3.1 definition: operating requirement......................................6 3.2 definition: operating behavior ...........................................7 3.3 definition: attribute ............................................................7 3.4 definition: rating ...............................................................8 3.5 result of exceeding a rating ..............................................8 3.6 relationship between ratings and operating requirements......................................................................8 3.7 guidelines for ratings and operating requirements............9 3.8 definition: typical value.....................................................9 3.9 typical value conditions .................................................... 10 4 ratings ...................................................................................... 10 4.1 thermal handling ratings ................................................... 11 4.2 moisture handling ratings .................................................. 11 4.3 esd handling ratings ......................................................... 11 4.4 voltage and current operating ratings ............................... 11 5 general ..................................................................................... 12 5.1 nonswitching electrical specifications ............................... 12 5.1.1 voltage and current operating requirements ...... 12 5.1.2 lvd and por operating requirements ............... 13 5.1.3 voltage and current operating behaviors ............ 14 5.1.4 power mode transition operating behaviors ....... 15 5.1.5 power consumption operating behaviors............16 5.1.6 emc radiated emissions operating behaviors .... 20 5.1.7 designing with radiated emissions in mind ......... 21 5.1.8 capacitance attributes ........................................ 21 5.2 switching specifications.....................................................21 5.2.1 device clock specifications ................................. 21 5.2.2 general switching specifications.........................22 5.3 thermal specifications ....................................................... 23 5.3.1 thermal operating requirements.........................23 5.3.2 thermal attributes ............................................... 23 6 peripheral operating requirements and behaviors .................... 24 6.1 core modules .................................................................... 24 6.1.1 debug trace timing specifications ....................... 24 6.1.2 jtag electricals..................................................25 6.2 system modules ................................................................ 28 6.3 clock modules ................................................................... 28 6.3.1 mcg specifications ............................................. 28 6.3.2 oscillator electrical specifications ....................... 31 6.3.3 32khz oscillator electrical characteristics ......... 33 6.4 memories and memory interfaces ..................................... 34 6.4.1 flash (ftfl) electrical specifications ................. 34 6.4.2 ezport switching specifications ......................... 38 6.4.3 flexbus switching specifications........................39 6.5 security and integrity modules .......................................... 42 6.6 analog ............................................................................... 42 6.6.1 adc electrical specifications .............................. 42 6.6.2 cmp and 6-bit dac electrical specifications ...... 50 6.6.3 12-bit dac electrical characteristics ................... 52 6.6.4 voltage reference electrical specifications..........55 6.7 timers................................................................................56 6.8 communication interfaces ................................................. 57 6.8.1 ethernet switching specifications ........................ 57 6.8.2 usb electrical specifications...............................59 6.8.3 usb dcd electrical specifications ...................... 59 6.8.4 usb vreg electrical specifications ................... 59 6.8.5 can switching specifications .............................. 60 6.8.6 dspi switching specifications (low-speed mode)..................................................................60 6.8.7 dspi switching specifications (high-speed mode)..................................................................62 6.8.8 i2c switching specifications ................................ 63 6.8.9 uart switching specifications............................63 6.8.10 sdhc specifications ........................................... 63 6.8.11 i2s switching specifications ................................ 64 6.9 human-machine interfaces (hmi)......................................66 6.9.1 tsi electrical specifications ................................ 66 7 dimensions ............................................................................... 67 7.1 obtaining package dimensions ......................................... 67 8 pinout ........................................................................................ 68 k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 3
8.1 k60 signal multiplexing and pin assignments .................. 68 8.2 k60 pinouts ....................................................................... 72 9 revision history ........................................................................ 73 k60 sub-family data sheet data sheet, rev. 5, 5/2011. 4 preliminary freescale semiconductor, inc.
1 ordering parts 1.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers: pk60 and mk60. 2 part identification 2.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 2.2 format part numbers for this device have the following format: q k## a m fff r t pp cc n 2.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification k## kinetis family ? k60 a key attribute ? d = cortex-m4 w/ dsp ? f = cortex-m4 w/ dsp and fpu m flash memory type ? n = program flash only ? x = program flash and flexmemory table continues on the next page... ordering parts k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 5
field description values fff program flash memory size ? 32 = 32 kb ? 64 = 64 kb ? 128 = 128 kb ? 256 = 256 kb ? 512 = 512 kb ? 1m0 = 1 mb r silicon revision ? z = initial ? (blank) = main ? a = revision after main t temperature range (c) ? v = C40 to 105 ? c = C40 to 85 pp package identifier ? fm = 32 qfn (5 mm x 5 mm) ? ft = 48 qfn (7 mm x 7 mm) ? lf = 48 lqfp (7 mm x 7 mm) ? ex = 64 qfn (9 mm x 9 mm) ? lh = 64 lqfp (10 mm x 10 mm) ? lk = 80 lqfp (12 mm x 12 mm) ? mb = 81 mapbga (8 mm x 8 mm) ? ll = 100 lqfp (14 mm x 14 mm) ? mc = 121 mapbga (8 mm x 8 mm) ? lq = 144 lqfp (20 mm x 20 mm) ? md = 144 mapbga (13 mm x 13 mm) ? mf = 196 mapbga (15 mm x 15 mm) ? mj = 256 mapbga (17 mm x 17 mm) cc maximum cpu frequency (mhz) ? 5 = 50 mhz ? 7 = 72 mhz ? 10 = 100 mhz ? 12 = 120 mhz ? 15 = 150 mhz n packaging type ? r = tape and reel ? (blank) = trays 2.4 example this is an example part number: mk60dn512zvmd10 3 terminology and guidelines terminology and guidelines k60 sub-family data sheet data sheet, rev. 5, 5/2011. 6 preliminary freescale semiconductor, inc.
3.1 definition: operating requirement an operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 3.1.1 example this is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: symbol description min. max. unit v dd 1.0 v core supply voltage 0.9 1.1 v 3.2 definition: operating behavior an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.1 example this is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: symbol description min. max. unit i wp digital i/o weak pullup/ pulldown current 10 130 a 3.3 definition: attribute an attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. terminology and guidelines k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 7
3.3.1 example this is an example of an attribute: symbol description min. max. unit cin_d input capacitance: digital pins 7 pf 3.4 definition: rating a rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. 3.4.1 example this is an example of an operating rating: symbol description min. max. unit v dd 1.0 v core supply voltage C0.3 1.2 v 3.5 result of exceeding a rating 40 30 20 10 0 measured characteristic operating rating failures in time (ppm) the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. terminology and guidelines k60 sub-family data sheet data sheet, rev. 5, 5/2011. 8 preliminary freescale semiconductor, inc.
3.6 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range limited operating range - no permanent failure - possible decreased life - possible incorrect operation fatal range - probable permanent failure limited operating range - no permanent failure - possible decreased life - possible incorrect operation handling range - no permanent failure fatal range - probable permanent failure operating or handling rating (max.) operating requirement (max.) operating requirement (min.) operating or handling rating (min.) 3.7 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 3.8 definition: typical value a typical value is a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions typical values are provided as design guidelines and are neither tested nor guaranteed. 3.8.1 example 1 this is an example of an operating behavior that includes a typical value: terminology and guidelines k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 9
symbol description min. typ. max. unit i wp digital i/o weak pullup/pulldown current 10 70 130 a 3.8.2 example 2 this is an example of a chart that shows typical values for various voltage and temperature conditions: 0.90 0.95 1.00 1.05 1.10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 c 105 c 25 c C40 c v dd (v) i (a) dd_stop t j 3.9 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd 3.3 v supply voltage 3.3 v 4 ratings ratings k60 sub-family data sheet data sheet, rev. 5, 5/2011. 10 preliminary freescale semiconductor, inc.
4.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 solder temperature, leaded 245 1. determined according to jedec standard jesd22-a103, high temperature storage life. 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices. 4.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices. 4.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model -2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model -500 +500 v 2 i lat latch-up current at ambient temperature of 105c -100 +100 ma 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm). 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components. 4.4 voltage and current operating ratings symbol description min. max. unit v dd digital supply voltage C0.3 3.8 v i dd digital supply current 185 ma v dio digital input voltage (except reset, extal, and xtal) C0.3 5.5 v table continues on the next page... ratings k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 11
symbol description min. max. unit v aio analog 1 , reset, extal, and xtal input voltage C0.3 v dd + 0.3 v i d instantaneous maximum current single pin limit (applies to all port pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v v usb_dp usb_dp input voltage C0.3 3.63 v v usb_dm usb_dm input voltage C0.3 3.63 v vregin usb regulator input C0.3 6.0 v v bat rtc battery supply voltage C0.3 3.8 v 1. analog pins are defined as pins that do not have an associated general purpose i/o port function. 5 general 5.1 nonswitching electrical specifications 5.1.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd C v dda v dd -to-v dda differential voltage C0.1 0.1 v v ss C v ssa v ss -to-v ssa differential voltage C0.1 0.1 v v bat rtc battery supply voltage 1.71 3.6 v v ih input high voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis 0.06 v dd v i icdio digital pin negative dc injection current single pin ? v in < v ss -0.3v -5 ma 1 table continues on the next page... general k60 sub-family data sheet data sheet, rev. 5, 5/2011. 12 preliminary freescale semiconductor, inc.
table 1. voltage and current operating requirements (continued) symbol description min. max. unit notes i icaio analog 2 , extal, and xtal pin dc injection current single pin ? v in < v ss -0.3v (negative current injection) ? v in > v dd +0.3v (positive current injection) -5 +5 ma 3 i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins ? negative current injection ? positive current injection -25 +25 ma v ram v dd voltage required to retain ram 1.2 v v rfvbat v bat voltage required to retain the vbat register file tbd v 1. all 5 volt tolerant digital i/o pins are internally clamped to v ss through a esd protection diode. there is no diode connection to v dd . if v in greater than v dio_min (=v ss -0.3v) is observed, then there is no need to provide current limiting resistors at the pads. if this limit cannot be observed then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v dio_min -v in )/|i ic |. 2. analog pins are defined as pins that do not have an associated general purpose i/o port function. 3. all analog pins are internally clamped to v ss and v dd through esd protection diodes. if v in is greater than v aio_min (=v ss -0.3v) and v in is less than v aio_max (=v dd +0.3v) is observed, then there is no need to provide current limiting resistors at the pads. if these limits cannot be observed then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v aio_min -v in )/|i ic |. the positive injection current limiting resistor is calcualted as r=(v in -v aio_max )/|i ic |. select the larger of these two calculated resistances. 5.1.2 lvd and por operating requirements table 2. v dd supply lvd and por operating requirements symbol description min. typ. max. unit notes v por falling vdd por detect voltage tbd 1.1 tbd v v lvdh falling low-voltage detect threshold high range (lvdv=01) tbd 2.56 tbd v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) tbd tbd tbd tbd 2.70 2.80 2.90 3.00 tbd tbd tbd tbd v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 60 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) tbd 1.60 tbd v table continues on the next page... general k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 13
table 2. v dd supply lvd and por operating requirements (continued) symbol description min. typ. max. unit notes v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) tbd tbd tbd tbd 1.80 1.90 2.00 2.10 tbd tbd tbd tbd v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 40 mv v bg bandgap voltage reference tbd 1.00 tbd v t lpo internal low power oscillator period factory trimmed tbd 1000 tbd s 1. rising thresholds are falling threshold + hysteresis voltage table 3. vbat power operating requirements symbol description min. typ. max. unit notes v por_vbat falling vbat supply por detect voltage tbd 1.1 tbd v 5.1.3 voltage and current operating behaviors table 4. voltage and current operating behaviors symbol description min. max. unit notes v oh output high voltage high drive strength ? 2.7 v v dd 3.6 v, i oh = -10ma ? 1.71 v v dd 2.7 v, i oh = -3ma v dd C 0.5 v dd C 0.5 v v output high voltage low drive strength ? 2.7 v v dd 3.6 v, i oh = -2ma ? 1.71 v v dd 2.7 v, i oh = -0.6ma v dd C 0.5 v dd C 0.5 v v i oht output high current total for all ports 100 ma v ol output low voltage high drive strength ? 2.7 v v dd 3.6 v, i ol = 10ma ? 1.71 v v dd 2.7 v, i ol = 3ma 0.5 0.5 v v output low voltage low drive strength ? 2.7 v v dd 3.6 v, i ol = 2ma ? 1.71 v v dd 2.7 v, i ol = 0.6ma 0.5 0.5 v v table continues on the next page... general k60 sub-family data sheet data sheet, rev. 5, 5/2011. 14 preliminary freescale semiconductor, inc.
table 4. voltage and current operating behaviors (continued) symbol description min. max. unit notes i olt output low current total for all ports 100 ma i in input leakage current (per pin) for full temperature range 1 a 1 i in input leakage current (per pin) at 25c tbd a 1 i oz hi-z (off-state) leakage current (per pin) 1 a r pu internal pullup resistors 20 50 k 2 r pd internal pulldown resistors 20 50 k 3 1. measured at vdd=3.6v 2. measured at v dd supply voltage = v dd min and vinput = v ss 3. measured at v dd supply voltage = v dd min and vinput = v dd 5.1.4 power mode transition operating behaviors all specifications except t por , and vllsxrun recovery times in the following table assume this clock configuration: ? cpu and system clocks = 100 mhz ? bus clock = 50 mhz ? flexbus clock = 50 mhz ? flash clock = 25 mhz table 5. power mode transition operating behaviors symbol description min. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.71 v to execution of the first instruction across the operating temperature range of the chip. 300 s 1 run vlls1 run ? run vlls1 ? vlls1 run 4.1 123.8 s s run vlls2 run ? run vlls2 ? vlls2 run 4.1 49.3 s s run vlls3 run ? run vlls3 ? vlls3 run 4.1 49.2 s s table continues on the next page... general k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 15
table 5. power mode transition operating behaviors (continued) symbol description min. max. unit notes run lls run ? run lls ? lls run 4.1 5.9 s s run stop run ? run stop ? stop run 4.1 4.2 s s run vlps run ? run vlps ? vlps run 4.1 5.8 s s 1. normal boot (ftfl_opt[lpboot]=1) 5.1.5 power consumption operating behaviors table 6. power consumption operating behaviors symbol description min. typ. max. unit notes i dda analog supply current tbd ma 1 i dd_run run mode current all peripheral clocks disabled, code executing from flash ? @ 1.8v ? @ 3.0v 40 42 tbd tbd ma ma 2 i dd_run run mode current all peripheral clocks enabled, code executing from flash ? @ 1.8v ? @ 3.0v 55 56 tbd tbd ma ma 3 i dd_run_m ax run mode current all peripheral clocks enabled and peripherals active, code executing from flash ? @ 1.8v ? @ 3.0v ? @ 25c ? @ 125c 66 66 tbd tbd tbd tbd ma ma ma 4 i dd_wait wait mode high frequency current at 3.0 v all peripheral clocks disabled 35 tbd ma 2 i dd_wait wait mode reduced frequency current at 3.0 v all peripheral clocks disabled 15 tbd ma 5 table continues on the next page... general k60 sub-family data sheet data sheet, rev. 5, 5/2011. 16 preliminary freescale semiconductor, inc.
table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_stop stop mode current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 0.4 tbd tbd tbd tbd tbd ma ma ma i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks disabled 1.25 tbd ma 6 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks enabled tbd tbd ma 7 i dd_vlpw very-low-power wait mode current at 3.0 v 1.05 tbd ma 8 i dd_vlps very-low-power stop mode current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 50 tbd tbd tbd tbd tbd a a a i dd_lls low leakage stop mode current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 12 tbd tbd tbd tbd tbd a a a 9 i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 8 tbd tbd tbd tbd tbd a a a 9 i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 4 tbd tbd tbd tbd tbd a a a i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 2 tbd tbd tbd tbd tbd a a a i dd_vbat average current when cpu is not accessing rtc registers at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 0.7 tbd tbd tbd tbd tbd a a a 10 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module's specification for its supply current. general k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 17
2. 100mhz core and system clock, 50mhz bus and flexbus clock, and 25mhz flash clock . mcg configured for fei mode. all peripheral clocks disabled. 3. 100mhz core and system clock, 50mhz bus and flexbus clock, and 25mhz flash clock. mcg configured for fei mode. all peripheral clocks enabled, but peripherals are not in active operation. 4. 100mhz core and system clock, 50mhz bus and flexbus clock, and 25mhz flash clock. mcg configured for fei mode. all peripheral clocks enabled, and peripherals are in active operation. 5. 25mhz core and system clock, 25mhz bus clock, and 12.5mhz flexbus and flash clock. mcg configured for fei mode. 6. 2 mhz core, system, flexbus, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. code executing from flash. 7. 2 mhz core, system, flexbus, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks enabled but peripherals are not in active operation. code executing from flash. 8. 2 mhz core, system, flexbus, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. 9. data reflects devices with 128 kb of ram. for devices with 64 kb of ram, power consumption is reduced by 2 a. 10. includes 32khz oscillator current and rtc operation. 5.1.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg in fei mode (39.0625 khz irc), except for 1 mhz core (fbe) ? all peripheral clocks disabled except ftfl ? lvd disabled, usb regulator disabled ? no gpios toggled ? code execution from flash general k60 sub-family data sheet data sheet, rev. 5, 5/2011. 18 preliminary freescale semiconductor, inc.
figure 1. run mode supply current vs. core frequency all peripheral clocks disabled the following data was measured under these conditions: ? mcg in fei mode (39.0625 khz irc), except for 1 mhz core (fbe) ? all peripheral clocks enabled but peripherals are not in active operation ? lvd disabled, usb regulator disabled ? no gpios toggled ? code execution from flash general k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 19
figure 2. run mode supply current vs. core frequency all peripheral clocks enabled 5.1.6 emc radiated emissions operating behaviors table 7. emc radiated emissions operating behaviors symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.15C50 tbd dbv 1, 2 v re2 radiated emissions voltage, band 2 50C150 tbd dbv v re3 radiated emissions voltage, band 3 150C500 tbd dbv v re4 radiated emissions voltage, band 4 500C1000 tbd dbv v re_iec_sae iec and sae level 0.15C1000 tbd 2, 3 1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions, iec standard 61967-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method, and sae standard j1752-3, measurement of radiated emissions from integrated circuitstem/ wideband tem (gtem) cell method. 2. v dd = 3 v, t a = 25 c, f osc = 12 mhz (crystal), f sys = 96 mhz general k60 sub-family data sheet data sheet, rev. 5, 5/2011. 20 preliminary freescale semiconductor, inc.
3. specified according to annex d of iec standard 61967-2, measurement of radiated emissionstem cell and wideband tem cell method, and appendix d of sae standard j1752-3, measurement of radiated emissions from integrated circuitstem/wideband tem (gtem) cell method. 5.1.7 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to http://www.freescale.com. 2. perform a keyword search for emc design. 5.1.8 capacitance attributes table 8. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf c in_d input capacitance: digital pins 7 pf 5.2 switching specifications 5.2.1 device clock specifications table 9. device clock specifications symbol description min. max. unit notes normal run mode f sys system and core clock 100 mhz f sys_usb system and core clock when full speed usb in operation 20 mhz f enet system and core clock when ethernet in operation tbd mhz f bus bus clock 50 mhz fb_clk flexbus clock 50 mhz f flash flash clock 25 mhz f lptmr lptmr clock 25 mhz vlpr mode f sys system and core clock 2 mhz f bus bus clock 2 mhz table continues on the next page... general k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 21
table 9. device clock specifications (continued) symbol description min. max. unit notes fb_clk flexbus clock 2 mhz f flash flash clock 1 mhz f lptmr lptmr clock 25 mhz 5.2.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, uart, can, cmt, ieee 1588 timer, and i 2 c signals. table 10. general switching specifications symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) asynchronous path 100 ns 2 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) asynchronous path 16 ns 2 external reset pulse width (digital glitch filter disabled) 100 ns 2 mode select ( ezp_cs) hold time after reset deassertion 2 bus clock cycles port rise and fall time (high drive strength) ? slew disabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew enabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v 12 tbd 36 tbd ns ns ns ns 3 port rise and fall time (low drive strength) ? slew disabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew enabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v 32 tbd 36 tbd ns ns ns ns 4 general k60 sub-family data sheet data sheet, rev. 5, 5/2011. 22 preliminary freescale semiconductor, inc.
1. the greater synchronous and asynchronous timing must be met. 2. this is the shortest pulse that is guaranteed to be recognized. 3. 75pf load 4. 15pf load 5.3 thermal specifications 5.3.1 thermal operating requirements table 11. thermal operating requirements symbol description min. max. unit t j die junction temperature C40 125 c t a ambient temperature C40 105 c 5.3.2 thermal attributes board type symbol description 100 lqfp unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) tbd c/w 1 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) tbd c/w 1 single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./ min. air speed) tbd c/w 1 four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./ min. air speed) tbd c/w 1 r jb thermal resistance, junction to board tbd c/w 2 r jc thermal resistance, junction to case tbd c/w 3 table continues on the next page... general k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 23
board type symbol description 100 lqfp unit notes jt thermal characterization parameter, junction to package top outside center (natural convection) tbd c/w 4 1. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air), or eia/jedec standard jesd51-6, integrated circuit thermal test method environmental conditionsforced convection (moving air). 2. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditionsjunction-to-board. 3. determined according to method 1012.1 of mil-std 883, test method standard, microcircuits, with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air). 6 peripheral operating requirements and behaviors all digital i/o switching characteristics assume: 1. output pins ? have c l =30pf loads, ? are configured for fast slew rate (portx_pcrn[sre]=0), and ? are configured for high drive strength (portx_pcrn[dse]=1) 2. input pins ? have their passive filter disabled (portx_pcrn[pfe]=0) 6.1 core modules 6.1.1 debug trace timing specifications table 12. debug trace operating behaviors symbol description min. max. unit t cyc clock period frequency dependent mhz t wl low pulse width 2 ns t wh high pulse width 2 ns t r clock and data rise time 3 ns t f clock and data fall time 3 ns table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 24 preliminary freescale semiconductor, inc.
table 12. debug trace operating behaviors (continued) symbol description min. max. unit t s data setup 3 ns t h data hold 2 ns figure 3. trace_clkout specifications th ts ts th trace_clkout trace_d[3:0] figure 4. trace data specifications 6.1.2 jtag electricals table 13. jtag limited voltage range electricals symbol description min. max. unit operating voltage 2.7 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag ? serial wire debug 0 0 0 10 25 50 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width ? boundary scan ? jtag and cjtag ? serial wire debug 50 20 10 ns ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 0 ns table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 25
table 13. jtag limited voltage range electricals (continued) symbol description min. max. unit j7 tclk low to boundary scan output data valid 25 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1 ns j11 tclk low to tdo data valid 17 ns j12 tclk low to tdo high-z 17 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns table 14. jtag full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag ? serial wire debug 0 0 0 10 20 40 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width ? boundary scan ? jtag and cjtag ? serial wire debug 50 25 12.5 ns ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 0 ns j7 tclk low to boundary scan output data valid 25 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1.4 ns j11 tclk low to tdo data valid 22.1 ns j12 tclk low to tdo high-z 22.1 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 26 preliminary freescale semiconductor, inc.
j2 j3 j3 j4 j4 tclk (input) figure 5. test clock input timing j7 j8 j7 j5 j6 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs figure 6. boundary scan (jtag) timing peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 27
j11 j12 j11 j9 j10 input data valid output data valid output data valid tclk tdi/tms tdo tdo tdo figure 7. test access port timing j14 j13 tclk trst figure 8. trst timing 6.2 system modules there are no specifications necessary for the device's system modules. 6.3 clock modules peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 28 preliminary freescale semiconductor, inc.
6.3.1 mcg specifications table 15. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal vdd and 25c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz i ints internal reference (slow clock) current tbd a t irefsts internal reference (slow clock) startup time tbd 4 s 1 fdco_res_t resolution of trimmed dco output frequency at fixed voltage and temperature using sctrim and scftrim 0.1 0.3 %f dco 2 f dco_res_t resolution of trimmed dco output frequency at fixed voltage and temperature using sctrim only 0.2 0.5 %f dco 2 f dco_t total deviation of trimmed average dco output frequency over voltage and temperature + 0.5 - 1.0 3.5 %f dco 2 f dco_t total deviation of trimmed average dco output frequency over fixed voltage and temperature range of 0C70c 0.5 tbd %f dco 2 f intf_ft internal reference frequency (fast clock) factory trimmed at nominal vdd and 25c 3.4 4 mhz f intf_t internal reference frequency (fast clock) user trimmed 3 5 mhz i intf internal reference (fast clock) current tbd a t irefstf internal reference startup time (fast clock) tbd tbd s 1 f loc_low loss of external clock minimum frequency range = 00 (3/5) x f ints_t khz f loc_high loss of external clock minimum frequency range = 01, 10, or 11 (16/5) x f ints_t khz fll f fll_ref fll reference frequency range 31.25 39.0625 khz f dco dco output frequency range low range (drs=00) 640 f fll_ref 20 20.97 25 mhz 3, 4 mid range (drs=01) 1280 f fll_ref 40 41.94 50 mhz mid-high range (drs=10) 1920 f fll_ref 60 62.91 75 mhz high range (drs=11) 2560 f fll_ref 80 83.89 100 mhz table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 29
table 15. mcg specifications (continued) symbol description min. typ. max. unit notes f dco_t_dmx3 2 dco output frequency low range (drs=00) 732 f fll_ref 23.99 mhz 5, 6 mid range (drs=01) 1464 f fll_ref 47.97 mhz mid-high range (drs=10) 2197 f fll_ref 71.99 mhz high range (drs=11) 2929 f fll_ref 95.98 mhz j cyc_fll fll period jitter tbd tbd ps 7 j acc_fll fll accumulated jitter of dco output over a 1s time window tbd tbd ps 7 t fll_acquire fll target frequency acquisition time 1 ms 8 pll f vco vco operating frequency 48.0 100 mhz i pll pll operating current ? pll @ 96 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 48) 1060 a 9 i pll pll operating current ? pll @ 48 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 24) 600 a 9 f pll_ref pll reference frequency range 2.0 4.0 mhz j cyc_pll pll period jitter (rms) ? f vco = 48 mhz ? f vco = 100 mhz 120 50 ps ps 10 j acc_pll pll accumulated jitter over 1s (rms) ? f vco = 48 mhz ? f vco = 100 mhz 1350 600 ps ps 10 d lock lock entry frequency tolerance 1.49 2.98 % d unl lock exit frequency tolerance 4.47 5.97 % t pll_lock lock detector detection time 0.15 + 1075(1/ f pll_ref ) ms 11 1. the startup time is defined as the time between the irc being enabled, either by the mcg or by the irclken bit being set, and the first edge of the internal reference clock. 2. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 3. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 4. the resulting system clock frequencies should not exceed their maximum specified values. the dco frequency deviation (f dco_t ) over voltage and temperature should be considered. peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 30 preliminary freescale semiconductor, inc.
5. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=1. 6. the resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. this specification was obtained at tbd frequency. 8. this specification applies to any time the fll reference source or reference divider is changed, trim value is changed, dmx32 bit is changed, drs bits are changed, or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. excludes any oscillator currents that are also consuming power while pll is in operation. 10. this specification was obtained using a freescale developed pcb. pll jitter is dependent on the noise characteristics of each pcb and results will vary. 11. this specification applies to any time the pll vco divider or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 6.3.2 oscillator electrical specifications this section provides the electrical characteristics of the module. 6.3.2.1 oscillator dc electrical specifications table 16. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) ? 32 khz ? 4 mhz ? 8 mhz (only range=01) ? 16 mhz ? 24 mhz ? 32 mhz 500 200 300 950 1.2 1.5 na a a a ma ma 1 i ddosc supply current high gain mode (hgo=1) ? 32 khz ? 4 mhz ? 8 mhz (only range=01) ? 16 mhz ? 24 mhz ? 32 mhz 25 400 500 2.5 3 4 a a a ma ma ma 1 c x extal load capacitance 2, 3 c y xtal load capacitance 2, 3 table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 31
table 16. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes r f feedback resistor low-frequency, low-power mode (hgo=0) m 2, 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m feedback resistor high-frequency, low-power mode (hgo=0) m feedback resistor high-frequency, high-gain mode (hgo=1) 1 m r s series resistor low-frequency, low-power mode (hgo=0) k series resistor low-frequency, high-gain mode (hgo=1) 200 k series resistor high-frequency, low-power mode (hgo=0) k series resistor high-frequency, high-gain mode (hgo=1) 0 k v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c 2. see crystal or resonator manufacturer's recommendation 3. c x ,c y can be provided by using either the integrated capacitors or by using external components. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 oscillator frequency specifications table 17. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low frequency mode (mcg_c2[range]=00) 32 40 khz table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 32 preliminary freescale semiconductor, inc.
table 17. oscillator frequency specifications (continued) symbol description min. typ. max. unit notes f osc_hi_1 oscillator crystal or resonator frequency high frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 50 mhz 1 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 750 ms 2, 3 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 250 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. other frequency limits may apply when external clock is being used as a reference for the fll or pll 2. proper pc board layout procedures must be followed to achieve specifications. 3. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. 6.3.3 32khz oscillator electrical characteristics this section describes the module electrical characteristics. 6.3.3.1 32khz oscillator dc electrical specifications table 18. 32khz oscillator dc electrical specifications symbol description min. typ. max. unit v bat supply voltage 1.71 3.6 v r f internal feedback resistor 100 m c para parasitical capacitance of extal32 and xtal32 2.5 pf c load internal load capacitance (programmable) 15 pf v pp 1 peak-to-peak amplitude of oscillation 0.6 v 1. the extal32 and xtal32 pins should only be connected to required oscillator components and must not be connected to any other devices. peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 33
6.3.3.2 32khz oscillator frequency specifications table 19. 32khz oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal 32.768 khz t start crystal start-up time 1000 ms 1 1. proper pc board layout procedures must be followed to achieve specifications. 6.4 memories and memory interfaces 6.4.1 flash (ftfl) electrical specifications this section describes the electrical characteristics of the ftfl module. 6.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 20. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 20 tbd s t hversscr sector erase high-voltage time 20 100 ms 1 t hversblk256k erase block high-voltage time for 256 kb 160 800 ms 1 1. maximum time based on expectations at cycling end-of-life. 6.4.1.2 flash timing specifications commands table 21. flash command timing specifications symbol description min. typ. max. unit notes t rd1blk256k read 1s block execution time ? 256 kb data flash 1.4 ms t rd1sec2k read 1s section execution time (flash sector) 40 s 1 t pgmchk program check execution time 35 s 1 t rdrsrc read resource execution time 35 s 1 t pgm4 program longword execution time 50 tbd s table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 34 preliminary freescale semiconductor, inc.
table 21. flash command timing specifications (continued) symbol description min. typ. max. unit notes t ersblk256k erase flash block execution time ? 256 kb data flash 160 800 ms 2 t ersscr erase flash sector execution time 20 100 ms 2 t pgmsec512 t pgmsec1k t pgmsec2k program section execution time ? 512 b flash ? 1 kb flash ? 2 kb flash tbd tbd tbd tbd tbd tbd ms ms ms t rd1all read 1s all blocks execution time 2.8 ms t rdonce read once execution time 35 s 1 t pgmonce program once execution time 50 tbd s t ersall erase all blocks execution time 320 1600 ms 2 t vfykey verify backdoor access key execution time 35 s 1 t swapx01 t swapx02 t swapx04 t swapx08 swap control execution time ? control code 0x01 ? control code 0x02 ? control code 0x04 ? control code 0x08 tbd tbd tbd tbd tbd tbd tbd tbd s s s s t pgmpart256k program partition for eeprom execution time ? 256 kb flexnvm 175 tbd ms t setram32k t setram256k set flexram function execution time: ? 32 kb eeprom backup ? 256 kb eeprom backup tbd tbd tbd tbd ms ms byte-write to flexram for eeprom operation t eewr8bers byte-write to erased flexram location execution time 100 tbd s 3 t eewr8b32k t eewr8b64k t eewr8b128k t eewr8b256k byte-write to flexram execution time: ? 32 kb eeprom backup ? 64 kb eeprom backup ? 128 kb eeprom backup ? 256 kb eeprom backup tbd tbd tbd tbd tbd 1.5 tbd 2.5 ms ms ms ms word-write to flexram for eeprom operation t eewr16bers word-write to erased flexram location execution time 100 tbd s table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 35
table 21. flash command timing specifications (continued) symbol description min. typ. max. unit notes t eewr16b32k t eewr16b64k t eewr16b128k t eewr16b256k word-write to flexram execution time: ? 32 kb eeprom backup ? 64 kb eeprom backup ? 128 kb eeprom backup ? 256 kb eeprom backup tbd tbd tbd tbd tbd 1.5 tbd 2.5 ms ms ms ms longword-write to flexram for eeprom operation t eewr32bers longword-write to erased flexram location execution time 200 tbd s t eewr32b32k t eewr32b64k t eewr32b128k t eewr32b256k longword-write to flexram execution time: ? 32 kb eeprom backup ? 64 kb eeprom backup ? 128 kb eeprom backup ? 256 kb eeprom backup tbd tbd tbd tbd tbd 2.7 tbd 3.7 ms ms ms ms 1. assumes 25mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 3. for byte-writes to an erased flexram location, the aligned word containing the byte must be erased. 6.4.1.3 flash (ftfl) current and power specfications table 22. flash (ftfl) current and power specfications symbol description typ. unit i dd_pgm worst case programming current in program flash 10 ma 6.4.1.4 reliability specifications table 23. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 tbd years 2 t nvmretp1k data retention after up to 1 k cycles 10 tbd years 2 t nvmretp100 data retention after up to 100 cycles 15 tbd years 2 n nvmcycp cycling endurance 10 k tbd cycles 3 data flash t nvmretd10k data retention after up to 10 k cycles 5 tbd years 2 t nvmretd1k data retention after up to 1 k cycles 10 tbd years 2 t nvmretd100 data retention after up to 100 cycles 15 tbd years 2 table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 36 preliminary freescale semiconductor, inc.
table 23. nvm reliability specifications (continued) symbol description min. typ. 1 max. unit notes n nvmcycd cycling endurance 10 k tbd cycles 3 flexram as eeprom t nvmretee100 data retention up to 100% of write endurance 5 tbd years 2 t nvmretee10 data retention up to 10% of write endurance 10 tbd years 2 t nvmretee1 data retention up to 1% of write endurance 15 tbd years 2 n nvmwree16 n nvmwree128 n nvmwree512 n nvmwree4k n nvmwree32k write endurance ? eeprom backup to flexram ratio = 16 ? eeprom backup to flexram ratio = 128 ? eeprom backup to flexram ratio = 512 ? eeprom backup to flexram ratio = 4096 ? eeprom backup to flexram ratio = 32,768 35 k 315 k 1.27 m 10 m 80 m tbd tbd tbd tbd tbd writes writes writes writes writes 4 1. typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to 25c. for additional information on how freescale defines typical data retention, please refer to engineering bulletin eb618. 2. data retention is based on t javg = 55c (temperature profile over the lifetime of the application). 3. cycling endurance represents number of program/erase cycles at -40c t j 125c. 4. write endurance represents the number of writes to each flexram location at -40c tj 125c influenced by the cycling endurance of the flexnvm (same value as data flash) and the allocated eeprom backup per subsystem. minimum value assumes all byte-writes to flexram. 6.4.1.5 write endurance to flexram for eeprom when the flexnvm partition code is not set to full data flash, the eeprom data set size can be set to any of several non-zero values. the bytes not assigned to data flash via the flexnvm partition code are used by the ftfl to obtain an effective endurance increase for the eeprom data. the built-in eeprom record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the eeprom data through a larger eeprom nvm storage space. while different partitions of the flexnvm are available, the intention is that a single choice for the flexnvm partition code and eeprom data set size is used throughout the entire lifetime of a given application. the eeprom endurance equation and graph shown below assume that only one configuration is ever used. writes_subsystem = write_efficiency n eeprom C 2 eeesplit eeesize eeesplit eeesize nvmcycd where peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 37
? writes_subsystem minimum number of writes to each flexram location for subsystem (each subsystem can have different endurance) ? eeprom allocated flexnvm for each eeprom subsystem based on depart; entered with program partition command ? eeesplit flexram split factor for subsystem; entered with the program partition command ? eeesize allocated flexram based on depart; entered with program partition command ? write_efficiency ? 0.25 for 8-bit writes to flexram ? 0.50 for 16-bit or 32-bit writes to flexram ? n nvmcycd data flash cycling endurance figure 9. eeprom backup writes to flexram peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 38 preliminary freescale semiconductor, inc.
6.4.2 ezport switching specifications table 24. ezport switching specifications num description min. max. unit operating voltage 1.71 3.6 v ep1 ezp_ck frequency of operation (all commands except read) f sys /2 mhz ep1a ezp_ck frequency of operation (read command) f sys /8 mhz ep2 ezp_cs negation to next ezp_cs assertion 2 x t ezp_ck ns ep3 ezp_cs input valid to ezp_ck high (setup) 5 ns ep4 ezp_ck high to ezp_cs input invalid (hold) 5 ns ep5 ezp_d input valid to ezp_ck high (setup) 2 ns ep6 ezp_ck high to ezp_d input invalid (hold) 5 ns ep7 ezp_ck low to ezp_q output valid (setup) 12 ns ep8 ezp_ck low to ezp_q output invalid (hold) 0 ns ep9 ezp_cs negation to ezp_q tri-state 12 ns ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ezp_ck ezp_cs ezp_q (output) ezp_d (input) figure 10. ezport timing diagram 6.4.3 flexbus switching specifications all processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, fb_clk. the fb_clk frequency may be the same as the internal system bus frequency or an integer divider of that frequency. peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 39
the following timing numbers indicate when data is latched or driven onto the external bus, relative to the flexbus output clock (fb_clk). all other timing relationships can be derived from these values. table 25. flexbus limited range switching specifications num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 50 mhz fb1 clock period 20 ns fb2 address, data, and control output valid 11.5 ns 1 fb3 address, data, and control output hold 0.5 ns 1 fb4 data and fb_ta input setup 8.5 ns 2 fb5 data and fb_ta input hold 0.5 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n, fb_cs n, fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. 2. specification is valid for all fb_ad[31:0] and fb_ta. table 26. flexbus full range switching specifications num description min. max. unit notes operating voltage 1.71 3.6 v frequency of operation tbd mhz fb1 clock period tbd ns fb2 address, data, and control output valid 13.5 ns 1 fb3 address, data, and control output hold 0 ns 1 fb4 data and fb_ta input setup 13.7 ns 2 fb5 data and fb_ta input hold 0.5 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n, fb_cs n, fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. 2. specification is valid for all fb_ad[31:0] and fb_ta. peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 40 preliminary freescale semiconductor, inc.
address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb5 fb4 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] figure 11. flexbus read timing diagram peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 41
address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] figure 12. flexbus write timing diagram 6.5 security and integrity modules there are no specifications necessary for the device's security and integrity modules. 6.6 analog peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 42 preliminary freescale semiconductor, inc.
6.6.1 adc electrical specifications the 16-bit accuracy specifications listed in table 27 and table 28 are achievable on the differential pins adcx_dp0, adcx_dm0, adcx_dp1, adcx_dm1, adcx_dp3, and adcx_dm3. the adcx_dp2 and adcx_dm2 adc inputs are connected to the pga outputs and are not direct device pins. accuracy specifications for these pins are defined in table 29 and table 30. all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit adc operating conditions table 27. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd - v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss - v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high 1.13 v dda v dda v v refl reference voltage low v ssa v ssa v ssa v v adin input voltage v refl v refh v c adin input capacitance ? 16 bit modes ? 8/10/12 bit modes 8 4 10 5 pf r adin input resistance 2 5 k r as analog source resistance 13/12 bit modes f adck < 4mhz 5 k 3 f adck adc conversion clock frequency 13 bit modes 1.0 18.0 mhz 4 f adck adc conversion clock frequency 16 bit modes 2.0 12.0 mhz 5 table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 43
table 27. 16-bit adc operating conditions (continued) symbol description conditions min. typ. 1 max. unit notes c rate adc conversion rate 13 bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps 6 c rate adc conversion rate 16 bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 7 1. typical values assume v dda = 3.0 v, temp = 25c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. the analog source resistance should be kept as low as possible in order to achieve the best results. the results in this datasheet were derived from a system which has <8 analog source resistance. the r as / c as time constant should be kept to <1ns. 4. in order to use the maximum adc conversion clock frequency adhsc bit should be set and the adlpc should be clear. 5. in order to use the maximum adc conversion clock frequency adhsc bit should be set and the adlpc should be clear. 6. for guidelines and examples of conversion rate calculation please download the adc calculator tool http:// cache.freescale.com/files/soft_dev_tools/software/app_software/converters/adc_calculator_cnv.zip?fpsp=1 7. for guidelines and examples of conversion rate calculation please download the adc calculator tool http:// cache.freescale.com/files/soft_dev_tools/software/app_software/converters/adc_calculator_cnv.zip?fpsp=1 r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage due to input protection input pin input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 13. adc input impedance equivalency diagram peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 44 preliminary freescale semiconductor, inc.
6.6.1.2 16-bit adc electrical characteristics table 28. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source ? adlpc=1, adhsc=0 ? adlpc=1, adhsc=1 ? adlpc=0, adhsc=0 ? adlpc=0, adhsc=1 1.2 3.0 2.4 4.4 2.4 4.0 5.2 6.2 3.9 7.3 6.1 9.5 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 13 bit modes ? <12 bit modes 0.8 0.5 tbd 1 lsb 4 adc conversion clock <12mhz, max hardware averaging (avge = %1, avgs = %11) dnl differential non- linearity ? 13 bit modes ? <12 bit modes 0.7 0.2 tbd 0.5 lsb 4 adc conversion clock <12mhz, max hardware averaging (avge = %1, avgs = %11) inl integral non- linearity ? 13 bit modes ? <12 bit modes 1.0 0.5 tbd tbd lsb 4 max averaging e fs full-scale error ? 13 bit modes ? <12 bit modes 0.4 1.0 tbd tbd lsb 4 v adin = v dda e q quantization error ? 16 bit modes ? 13 bit modes -1 to 0 0.5 lsb 4 enob effective number of bits 16 bit differential mode ? avg=32 ? avg=1 16 bit single-ended mode ? avg=32 ? avg=1 tbd tbd tbd tbd 13.6 13.2 tbd tbd bits bits bits bits 5 table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 45
table 28. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16 bit differential mode ? avg=32 16 bit single-ended mode ? avg=32 C94 tbd tbd tbd db db 5 sfdr spurious free dynamic range 16 bit differential mode ? avg=32 16 bit single-ended mode ? avg=32 tbd tbd 95 tbd db db 5 e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope ? C40c to 105c tbd mv/c v temp25 temp sensor voltage 25c tbd mv 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and the adlpc bit (low power). for lowest power operation the adlpc bit should be set, the hsc bit should be clear with 1mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. input data is 1 khz sine wave. figure tbd figure 14. typical tue vs. adc conversion rate 12-bit single-ended mode figure tbd figure 15. typical enob vs. averaging for 16-bit differential and 16-bit single-ended modes peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 46 preliminary freescale semiconductor, inc.
6.6.1.3 16-bit adc with pga operating conditions table 29. 16-bit adc with pga operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v refpga pga ref voltage vref_ou t vref_ou t vref_ou t v 2, 3 v adin input voltage v ssa v dda v v cm input common mode range v ssa v dda v r pgad differential input impedance gain = 1, 2, 4, 8 gain = 16, 32 gain = 64 128 64 32 k in+ to in- 4 r as analog source resistance 100 5 t s adc sampling time 1.25 s 6 c rate adc conversion rate 13 bit modes no adc hardware averaging continuous conversions enabled peripheral clock = 50 mhz 18.484 450 ksps 7 16 bit modes no adc hardware averaging continuous conversions enabled peripheral clock = 50 mhz 37.037 250 ksps 8 1. typical values assume v dda = 3.0 v, temp = 25c, f adck = 6 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. adc must be configured to use the internal voltage reference (vref_out) 3. pga reference is internally connected to the vref_out pin. if the user wishes to drive vref_out with a voltage other than the output of the vref module, the vref module must be disabled. 4. for single ended configurations the input impedance of the driven input is r pgad /2 5. the analog source resistance (r as ), external to mcu, should be kept as minimum as possible. increased r as causes drop in pga gain without affecting other performances. this is not dependent on adc clock frequency. 6. the minimum sampling time is dependent on input signal frequency and adc mode of operation. a minimum of 1.25s time should be allowed for f in =4 khz at 16-bit differential mode. recommended adc setting is: adlsmp=1, adlsts=2 at 8 mhz adc clock. 7. adc clock = 18 mhz, adlsmp = 1, adlst = 00, adhsc = 1 8. adc clock = 12 mhz, adlsmp = 1, adlst = 01, adhsc = 1 peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 47
6.6.1.4 16-bit adc with pga characteristics table 30. 16-bit adc with pga characteristics symbol description conditions min. typ. 1 max. unit notes i dda_pga supply current low power (adc_pga[pgalpb]=0) 420 tbd a 2 i dc_pga input dc current a 3 gain =1, v refpga =1.2v, v cm =0.5v 1.54 a gain =64, v refpga =1.2v, v cm =0.1v 0.57 a g gain 4 ? pgag=0 ? pgag=1 ? pgag=2 ? pgag=3 ? pgag=4 ? pgag=5 ? pgag=6 0.95 1.9 3.8 7.6 15.2 30.0 58.8 1 2 4 8 16 31.6 63.3 1.05 2.1 4.2 8.4 16.6 33.2 67.8 r as < 100 bw input signal bandwidth ? 16-bit modes ? < 16-bit modes 4 40 khz khz psrr power supply rejection ratio gain=1 tbd tbd db v dda = 3v 100mv, f vdda = 50hz, 60hz cmrr common mode rejection ratio ? gain=1 ? gain=64 tbd tbd tbd tbd db db v cm = 500mvpp, f vcm = 50hz, 100hz v ofs input offset voltage 0.2 tbd mv output offset = v ofs *(gain+1) t gsw gain switching settling time 10 s 5 dg/dt gain drift over temperature ? gain=1 ? gain=64 tbd tbd tbd tbd ppm/c ppm/c 0 to 50c dv ofs /dt offset drift over temperature gain=1 tbd tbd ppm/c 0 to 50c, adc averaging=32 dg/dv dda gain drift over supply voltage ? gain=1 ? gain=64 tbd tbd tbd tbd %/v %/v v dda from 1.71 to 3.6v table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 48 preliminary freescale semiconductor, inc.
table 30. 16-bit adc with pga characteristics (continued) symbol description conditions min. typ. 1 max. unit notes e il input leakage error all modes i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) v pp,diff maximum differential input signal swing where v x = v refpga 0.583 v 6 snr signal-to-noise ratio ? gain=1 ? gain=64 tbd tbd 83.0 57.5 db db 16-bit differential mode, average=32 thd total harmonic distortion ? gain=1 ? gain=64 tbd tbd 89.4 90.0 db db 16-bit differential mode, average=32, f in =500hz sfdr spurious free dynamic range ? gain=1 ? gain=64 tbd tbd 90.9 77.0 db db 16-bit differential mode, average=32, f in =500hz enob effective number of bits ? gain=1, average=4 ? gain=1, average=8 ? gain=64, average=4 ? gain=64, average=8 ? gain=1, average=32 ? gain=2, average=32 ? gain=4, average=32 ? gain=8, average=32 ? gain=16, average=32 ? gain=32, average=32 ? gain=64, average=32 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 12.3 12.7 8.4 8.7 13.3 13.1 12.5 11.8 11.1 10.2 9.3 bits bits bits bits bits bits bits bits bits bits bits 16-bit differential mode,f in =100h z sinad signal-to-noise plus distortion ratio see enob 6.02 enob + 1.76 db 1. typical values assume v dda =3.0v, temp=25c, f adck =6mhz unless otherwise stated. 2. this current is a pga module adder, in addition to and adc conversion currents. 3. between in+ and in-. the pga draws a dc current from the input terminals. the magnitude of the dc current is a strong function of input common mode voltage (v cm ) and the pga gain. 4. gain = 2 pgag 5. after changing the pga gain setting, a minimum of 2 adc+pga conversions should be ignored. peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 49
6. limit the input signal swing so that the pga does not saturate during operation. input signal swing is dependent on the pga reference voltage and gain setting. 6.6.2 cmp and 6-bit dac electrical specifications table 31. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 a i ddls supply current, low-speed mode (en=1, pmode=0) 20 a v ain analog input voltage v ss C 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 120 250 600 ns analog comparator initialization delay 2 40 s i dac6b 6-bit dac current adder (enabled) 7 a inl 6-bit dac integral non-linearity C0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd -0.6v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to dacen, vrsel, psel, msel, vosel) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 50 preliminary freescale semiconductor, inc.
0.04 0.05 0.06 0.07 0.08 p hystereris (v) 00 01 10 hystctr setting 0 0.01 0.02 0.03 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm 10 11 vin level (v) figure 16. typical hysteresis vs. vin level (vdd=3.3v, pmode=0) peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 51
0 08 0.1 0.12 0.14 0.16 0.18 p hystereris (v) 00 01 10 hystctr setting 0 0.02 0.04 0.06 0.08 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm p 10 11 vin level (v) figure 17. typical hysteresis vs. vin level (vdd=3.3v, pmode=1) 6.6.3 12-bit dac electrical characteristics 6.6.3.1 12-bit dac operating requirements table 32. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 1.71 3.6 v v dacr reference voltage 1.13 3.6 v 1 t a temperature ?40 105 c c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be vdda or the voltage output of the vref module (vref_out) 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 52 preliminary freescale semiconductor, inc.
6.6.3.2 12-bit dac operating behaviors table 33. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_daclp supply current low-power mode 150 a i dda_dach p supply current high-speed mode 700 a t daclp full-scale settling time (0x080 to 0xf7f) low- power mode 100 200 s 1 t dachp full-scale settling time (0x080 to 0xf7f) high- power mode 15 30 s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode and high-speed mode 0.7 1 s 1 v dacoutl dac output voltage range low high-speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high-speed mode, no load, dac set to 0xfff v dacr ?100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda > = 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 v/c 6 t ge temperature coefficient gain error tbd ppm of fsr/c a c offset aging coefficient tbd v/yr rop output resistance load = 3 k 250 sr slew rate -80h f7fh 80h ? high power (sp hp ) ? low power (sp lp ) 1.2 0.05 1.7 0.12 v/s ct channel to channel cross talk -80 db bw 3db bandwidth ? high power (sp hp ) ? low power (sp lp ) 550 40 khz 1. settling within 1 lsb 2. the inl is measured for 0+100mv to v dacr ?100 mv 3. the dnl is measured for 0+100 mv to v dacr ?100 mv 4. the dnl is measured for 0+100mv to v dacr ?100 mv with v dda > 2.4v 5. calculated by a best fit curve from v ss +100 mv to v dacr ?100 mv peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 53
6. vdda = 3.0v, reference select set for vdda (dacx_co:dacrfs = 1), high power mode(dacx_c0:lpen = 0), dac set to 0x800, temp range from -40c to 105c figure 18. typical inl error vs. digital code peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 54 preliminary freescale semiconductor, inc.
figure 19. offset at half scale vs. temperature 6.6.4 voltage reference electrical specifications table 34. vref full-range operating requirements symbol description min. max. unit notes v dda supply voltage 1.71 3.6 v t a temperature ?40 105 c c l output load capacitance 100 nf table 35. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim at nominal v dda and temperature=25c tbd 1.2 tbd v table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 55
table 35. vref full-range operating behaviors (continued) symbol description min. typ. max. unit notes v out voltage reference output with factory trim tbd tbd v v out voltage reference output user trim 1.198 1.202 v v step voltage reference trim step 0.5 mv v drift temperature drift (vmax -vmin across the full temperature range) 40 mv see figure 20 ac aging coefficient tbd ppm/year i bg bandgap only (mode_lv = 00) current tbd a i tr tight-regulation buffer (mode_lv =10) current 1.1 ma v load load regulation (mode_lv = 10) ? current = + 1.0 ma ? current = - 1.0 ma tbd tbd mv 1 t stup buffer startup time 100 s dc line regulation (power supply rejection) tbd mv C60 tbd db 1. load regulation voltage is the difference between the vref_out voltage with no load vs. voltage with defined load table 36. vref limited-range operating requirements symbol description min. max. unit notes t a temperature 0 50 c table 37. vref limited-range operating behaviors symbol description min. max. unit notes v out voltage reference output with factory trim tbd tbd v tbd figure 20. typical output vs.temperature tbd figure 21. typical output vs. vdd 6.7 timers see general switching specifications. peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 56 preliminary freescale semiconductor, inc.
6.8 communication interfaces 6.8.1 ethernet switching specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 6.8.1.1 mii signal switching specifications the following timing specs meet the requirements for mii style interfaces for a range of transceiver devices. table 38. mii signal switching specifications symbol description min. max. unit rxclk frequency 25 mhz mii1 rxclk pulse width high 35% 65% rxclk period mii2 rxclk pulse width low 35% 65% rxclk period mii3 rxd[3:0], rxdv, rxer to rxclk setup 5 ns mii4 rxclk to rxd[3:0], rxdv, rxer hold 5 ns txclk frequency 25 mhz mii5 txclk pulse width high 35% 65% txclk period mii6 txclk pulse width low 35% 65% txclk period mii7 txclk to txd[3:0], txen, txer invalid 2 ns mii8 txclk to txd[3:0], txen, txer valid 25 ns peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 57
mii7 mii8 valid data valid data valid data mii6 mii5 txclk (input) txd[n:0] txen txer figure 22. mii transmit signal timing diagram mii2 mii1 mii4 mii3 valid data valid data valid data rxclk (input) rxd[n:0] rxdv rxer figure 23. mii receive signal timing diagram 6.8.1.2 rmii signal switching specifications the following timing specs meet the requirements for rmii style interfaces for a range of transceiver devices. table 39. rmii signal switching specifications num description min. max. unit extal frequency (rmii input clock rmii_clk) 50 mhz rmii1 rmii_clk pulse width high 35% 65% rmii_clk period rmii2 rmii_clk pulse width low 35% 65% rmii_clk period rmii3 rxd[1:0], crs_dv, rxer to rmii_clk setup 4 ns rmii4 rmii_clk to rxd[1:0], crs_dv, rxer hold 2 ns rmii7 rmii_clk to txd[1:0], txen invalid 4 ns rmii8 rmii_clk to txd[1:0], txen valid 15 ns peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 58 preliminary freescale semiconductor, inc.
6.8.2 usb electrical specifications the usb electricals for the usb on-the-go module conform to the standards documented by the universal serial bus implementers forum. for the most up-to-date standards, visit http://www.usb.org. 6.8.3 usb dcd electrical specifications table 40. usb dcd electrical specifications symbol description min. typ. max. unit v dp_src usb_dp source voltage (up to 250 a) tbd tbd tbd v v lgc threshold voltage for logic high 0.8 2.0 v i dp_src usb_dp source current 7 10 13 a i dm_sink usb_dm sink current 50 100 150 a r dm_dwn d- pulldown resistance for data pin contact detect 14.25 24.8 k v dat_ref data detect voltage 0.25 tbd 0.4 v 6.8.4 usb vreg electrical specifications table 41. usb vreg electrical specifications symbol description min. typ. max. unit notes vregin input supply voltage 2.7 5.5 v i ddon quiescent current run mode, load current equal zero, input supply (vregin) > 3.6 v 120 tbd a i ddstby quiescent current standby mode, load current equal zero 1 tbd a i ddoff quiescent current shutdown mode ? vregin = 5.0 v and temperature=25c ? across operating voltage and temperature 500 tbd na a i loadrun maximum load current run mode 120 ma i loadstby maximum load current standby mode 1 ma v reg33out regulator output voltage input supply (vregin) > 3.6 v ? run mode ? standby mode 3 tbd 3.3 2.8 3.6 3.6 v v table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 59
table 41. usb vreg electrical specifications (continued) symbol description min. typ. max. unit notes v reg33out regulator output voltage input supply (vregin) < 3.6 v, pass-through mode tbd 3.6 v 1 c out external output capacitor 1.76 2.2 8.16 f esr external output capacitor equivalent series resistance 1 100 m i lim short circuit current tbd 290 tbd ma 1. operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to i load . 6.8.5 can switching specifications see general switching specifications. 6.8.6 dspi switching specifications (low-speed mode) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 42. master mode dspi timing (low-speed mode) num description min. max. unit notes operating voltage 1.71 3.6 v 1 frequency of operation 12.5 mhz ds1 dspi_sck output cycle time 4 x t bus ns ds2 dspi_sck output high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds3 dspi_pcsn valid to dspi_sck delay (t bus x 2) ? 4 ns 2 ds4 dspi_sck to dspi_pcsn invalid delay (t bus x 2) ? 4 ns 3 ds5 dspi_sck to dspi_sout valid 10 ns ds6 dspi_sck to dspi_sout invalid -2 ns ds7 dspi_sin to dspi_sck input setup 15 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the dspi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 60 preliminary freescale semiconductor, inc.
3. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 24. dspi classic spi timing master mode table 43. slave mode dspi timing (low-speed mode) num description min. max. unit operating voltage 1.71 3.6 v frequency of operation 6.25 mhz ds9 dspi_sck input cycle time 8 x t bus ns ds10 dspi_sck input high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds11 dspi_sck to dspi_sout valid 20 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 5 ns ds14 dspi_sck to dspi_sin input hold 15 ns ds15 dspi_ss active to dspi_sout driven 19 ns ds16 dspi_ss inactive to dspi_sout not driven 19 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 25. dspi classic spi timing slave mode peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 61
6.8.7 dspi switching specifications (high-speed mode) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 44. master mode dspi timing (high-speed mode) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 25 mhz ds1 dspi_sck output cycle time 2 x t bus ns ds2 dspi_sck output high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds3 dspi_pcsn valid to dspi_sck delay (t bus x 2) ? 2 ns 1 ds4 dspi_sck to dspi_pcsn invalid delay (t bus x 2) ? 2 ns 2 ds5 dspi_sck to dspi_sout valid 8.5 ns ds6 dspi_sck to dspi_sout invalid ?2 ns ds7 dspi_sin to dspi_sck input setup tbd ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 2. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 26. dspi classic spi timing master mode peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 62 preliminary freescale semiconductor, inc.
table 45. slave mode dspi timing (high-speed mode) num description min. max. unit operating voltage 2.7 3.6 v frequency of operation 12.5 mhz ds9 dspi_sck input cycle time 4 x t bus ns ds10 dspi_sck input high/low time (t sck /2) ? 2 (t sck /2 + 2 ns ds11 dspi_sck to dspi_sout valid 10 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 14 ns ds16 dspi_ss inactive to dspi_sout not driven 14 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 27. dspi classic spi timing slave mode 6.8.8 i 2 c switching specifications see general switching specifications. 6.8.9 uart switching specifications see general switching specifications. peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 63
6.8.10 sdhc specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. table 46. sdhc switching specifications num symbol description min. max. unit operating voltage 2.7 3.6 v card input clock sd1 fpp clock frequency (low speed) 0 400 khz fpp clock frequency (sd\sdio full speed) 0 25 mhz fpp clock frequency (mmc full speed) 0 20 mhz f od clock frequency (identification mode) 0 400 khz sd2 t wl clock low time 7 ns sd3 t wh clock high time 7 ns sd4 t tlh clock rise time 3 ns sd5 t thl clock fall time 3 ns sdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd6 t od sdhc output delay (output valid) -5 6.5 ns sdhc input / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd7 t isu sdhc input setup time 5 ns sd8 t ih sdhc input hold time 0 ns sd2 sd3 sd1 sd6 sd8 sd7 sdhc_clk output sdhc_cmd output sdhc_dat[3:0] input sdhc_cmd input sdhc_dat[3:0] figure 28. sdhc timing peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 64 preliminary freescale semiconductor, inc.
6.8.11 i 2 s switching specifications this section provides the ac timings for the i 2 s in master (clocks driven) and slave modes (clocks input). all timings are given for non-inverted serial clock polarity (tcr[tsckp] = 0, rcr[rsckp] = 0) and a non-inverted frame sync (tcr[tfsi] = 0, rcr[rfsi] = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (i2s_bclk) and/or the frame sync (i2s_fs) shown in the figures below. table 47. i 2 s master mode timing num description min. max. unit operating voltage 2.7 3.6 v s1 i2s_mclk cycle time 2 x t sys ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_bclk cycle time 5 x t sys ns s4 i2s_bclk pulse width high/low 45% 55% bclk period s5 i2s_bclk to i2s_fs output valid 15 ns s6 i2s_bclk to i2s_fs output invalid -2.5 ns s7 i2s_bclk to i2s_txd valid 15 ns s8 i2s_bclk to i2s_txd invalid -3 ns s9 i2s_rxd/i2s_fs input setup before i2s_bclk 20 ns s10 i2s_rxd/i2s_fs input hold after i2s_bclk 0 ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_bclk (output) i2s_fs (output) i2s_fs (input) i2s_txd i2s_rxd figure 29. i 2 s timing master mode peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 65
table 48. i 2 s slave mode timing num description min. max. unit operating voltage 2.7 3.6 v s11 i2s_bclk cycle time (input) 8 x t sys ns s12 i2s_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_fs input setup before i2s_bclk 10 ns s14 i2s_fs input hold after i2s_bclk 3 ns s15 i2s_bclk to i2s_txd/i2s_fs output valid 20 ns s16 i2s_bclk to i2s_txd/i2s_fs output invalid 0 ns s17 i2s_rxd setup before i2s_bclk 10 ns s18 i2s_rxd hold after i2s_bclk 2 ns s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_bclk (input) i2s_fs (output) i2s_fs (input) i2s_txd i2s_rxd figure 30. i 2 s timing slave modes 6.9 human-machine interfaces (hmi) 6.9.1 tsi electrical specifications table 49. tsi electrical specifications symbol description min. typ. max. unit notes v ddtsi operating voltage 1.71 3.6 v c ele target electrode capacitance range 1 20 500 pf 1 f refmax reference oscillator frequency 5.5 tbd mhz 2 f elemax electrode oscillator frequency 0.5 tbd mhz 3 table continues on the next page... peripheral operating requirements and behaviors k60 sub-family data sheet data sheet, rev. 5, 5/2011. 66 preliminary freescale semiconductor, inc.
table 49. tsi electrical specifications (continued) symbol description min. typ. max. unit notes c ref internal reference capacitor tbd 1 tbd pf v delta oscillator delta voltage tbd 600 tbd mv 4 i ref reference oscillator current source base current 1.133 tbd a 3, 5 i ele electrode oscillator current source base current 1.133 tbd a 3, 5 pres5 electrode capacitance measurement precision tbd tbd % 6 pres20 electrode capacitance measurement precision tbd tbd % 7 pres100 electrode capacitance measurement precision tbd tbd % 8 maxsens2 0 maximum sensitivity @ 20 pf electrode 0.003 0.25 ff/count 9 maxsens maximum sensitivity 0.003 ff/count 10 res resolution 16 bits t con20 response time @ 20 pf 8 15 25 s 11 i tsi_run current added in run mode 55 a i tsi_lp low power mode current adder 1.3 tbd a 12 1. the tsi module is functional with capacitance values outside this range. however, optimal performance is not guaranteed. 2. captrm=7, delvol=7, and fixed external capacitance of 20 pf. 3. captrm=0, delvol=2, and fixed external capacitance of 20 pf. 4. captrm=0, extchrg=9, and fixed external capacitance of 20 pf. 5. the programmable current source value is generated by multiplying the scanc[refchrg] value and the base current. 6. measured with a 5 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 8; iext = 16. 7. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 2; iext = 16. 8. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 16, nscn = 3; iext = 16. 9. measured with a 20 pf electrode, reference oscillator frequency of ~5 mhz (i ref = 5 a, refchrg = 4), ps = 128, nscn = 2; iext = 16 (extchrg = 15). 10. typical value depends on the configuration used. 11. time to do one complete measurement of the electrode. sensitivity resolution of 0.0133 pf, ps = 0, nscn = 0, 1 electrode, delvol = 2, extchrg = 15. 12. captrm=7, delvol=2, refchrg=0, extchrg=4, ps=7, nscn=0f, lpscnitv=f, lpo is selected (1 khz), and fixed external capacitance of 20 pf. data is captured with an average of 7 periods window. 7 dimensions 7.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to http://www.freescale.com and perform a keyword search for the drawings document number: dimensions k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 67
if you want the drawing for this package then use this document number 100-pin lqfp 98ass23308w 8 pinout 8.1 k60 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. 100 lqf p pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 1 pte0 adc1_se4a adc1_se4a pte0 spi1_pcs1 uart1_tx sdhc0_d1 i2c1_sda 2 pte1 adc1_se5a adc1_se5a pte1 spi1_sout uart1_rx sdhc0_d0 i2c1_scl 3 pte2 adc1_se6a adc1_se6a pte2 spi1_sck uart1_cts _b sdhc0_dcl k 4 pte3 adc1_se7a adc1_se7a pte3 spi1_sin uart1_rts _b sdhc0_cm d 5 pte4 disabled pte4 spi1_pcs0 uart3_tx sdhc0_d3 6 pte5 disabled pte5 spi1_pcs2 uart3_rx sdhc0_d2 7 pte6 disabled pte6 spi1_pcs3 uart3_cts _b i2s0_mclk i2s0_clkin 8 vdd vdd vdd 9 vss vss vss 10 usb0_dp usb0_dp usb0_dp 11 usb0_dm usb0_dm usb0_dm 12 vout33 vout33 vout33 13 vregin vregin vregin 14 adc0_dp1 adc0_dp1 adc0_dp1 15 adc0_dm1 adc0_dm1 adc0_dm1 16 adc1_dp1 adc1_dp1 adc1_dp1 17 adc1_dm1 adc1_dm1 adc1_dm1 18 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 19 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 20 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 pinout k60 sub-family data sheet data sheet, rev. 5, 5/2011. 68 preliminary freescale semiconductor, inc.
100 lqf p pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 21 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 22 vdda vdda vdda 23 vrefh vrefh vrefh 24 vrefl vrefl vrefl 25 vssa vssa vssa 26 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 27 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 28 xtal32 xtal32 xtal32 29 extal32 extal32 extal32 30 vbat vbat vbat 31 pte24 adc0_se17 adc0_se17 pte24 can1_tx uart4_tx ewm_out_ b 32 pte25 adc0_se18 adc0_se18 pte25 can1_rx uart4_rx ewm_in 33 pte26 disabled pte26 uart4_cts _b enet_1588 _clkin rtc_clko ut usb_clkin 34 pta0 jtag_tclk/ swd_clk/ ezp_clk tsi0_ch1 pta0 uart0_cts _b ftm0_ch5 jtag_tclk/ swd_clk ezp_clk 35 pta1 jtag_tdi/ ezp_di tsi0_ch2 pta1 uart0_rx ftm0_ch6 jtag_tdi ezp_di 36 pta2 jtag_tdo/ trace_sw o/ezp_do tsi0_ch3 pta2 uart0_tx ftm0_ch7 jtag_tdo/ trace_sw o ezp_do 37 pta3 jtag_tms/ swd_dio tsi0_ch4 pta3 uart0_rts _b ftm0_ch0 jtag_tms/ swd_dio 38 pta4 nmi_b/ ezp_cs_b tsi0_ch5 pta4 ftm0_ch1 nmi_b ezp_cs_b 39 pta5 disabled pta5 ftm0_ch2 rmii0_rxe r/ mii0_rxer cmp2_out i2s0_rx_bc lk jtag_trst 40 vdd vdd vdd 41 vss vss vss 42 pta12 cmp2_in0 cmp2_in0 pta12 can0_tx ftm1_ch0 rmii0_rxd1 /mii0_rxd1 i2s0_txd ftm1_qd_p ha 43 pta13 cmp2_in1 cmp2_in1 pta13 can0_rx ftm1_ch1 rmii0_rxd0 /mii0_rxd0 i2s0_tx_fs ftm1_qd_p hb 44 pta14 disabled pta14 spi0_pcs0 uart0_tx rmii0_crs_ dv/ mii0_rxdv i2s0_tx_bc lk pinout k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 69
100 lqf p pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 45 pta15 disabled pta15 spi0_sck uart0_rx rmii0_txen /mii0_txen i2s0_rxd 46 pta16 disabled pta16 spi0_sout uart0_cts _b rmii0_txd0 /mii0_txd0 i2s0_rx_fs 47 pta17 adc1_se17 adc1_se17 pta17 spi0_sin uart0_rts _b rmii0_txd1 /mii0_txd1 i2s0_mclk i2s0_clkin 48 vdd vdd vdd 49 vss vss vss 50 pta18 extal extal pta18 ftm0_flt2 ftm_clkin 0 51 pta19 xtal xtal pta19 ftm1_flt0 ftm_clkin 1 lpt0_alt1 52 reset_b reset_b reset_b 53 ptb0 /adc0_se8/ adc1_se8/ tsi0_ch0 /adc0_se8/ adc1_se8/ tsi0_ch0 ptb0 i2c0_scl ftm1_ch0 rmii0_mdio /mii0_mdio ftm1_qd_p ha 54 ptb1 /adc0_se9/ adc1_se9/ tsi0_ch6 /adc0_se9/ adc1_se9/ tsi0_ch6 ptb1 i2c0_sda ftm1_ch1 rmii0_mdc/ mii0_mdc ftm1_qd_p hb 55 ptb2 / adc0_se12/ tsi0_ch7 / adc0_se12/ tsi0_ch7 ptb2 i2c0_scl uart0_rts _b enet0_158 8_tmr0 ftm0_flt3 56 ptb3 / adc0_se13/ tsi0_ch8 / adc0_se13/ tsi0_ch8 ptb3 i2c0_sda uart0_cts _b enet0_158 8_tmr1 ftm0_flt0 57 ptb9 ptb9 spi1_pcs1 uart3_cts _b fb_ad20 58 ptb10 /adc1_se14 /adc1_se14 ptb10 spi1_pcs0 uart3_rx fb_ad19 ftm0_flt1 59 ptb11 /adc1_se15 /adc1_se15 ptb11 spi1_sck uart3_tx fb_ad18 ftm0_flt2 60 vss vss vss 61 vdd vdd vdd 62 ptb16 /tsi0_ch9 /tsi0_ch9 ptb16 spi1_sout uart0_rx fb_ad17 ewm_in 63 ptb17 /tsi0_ch10 /tsi0_ch10 ptb17 spi1_sin uart0_tx fb_ad16 ewm_out_ b 64 ptb18 /tsi0_ch11 /tsi0_ch11 ptb18 can0_tx ftm2_ch0 i2s0_tx_bc lk fb_ad15 ftm2_qd_p ha 65 ptb19 /tsi0_ch12 /tsi0_ch12 ptb19 can0_rx ftm2_ch1 i2s0_tx_fs fb_oe_b ftm2_qd_p hb 66 ptb20 ptb20 spi2_pcs0 fb_ad31 cmp0_out 67 ptb21 ptb21 spi2_sck fb_ad30 cmp1_out 68 ptb22 ptb22 spi2_sout fb_ad29 cmp2_out 69 ptb23 ptb23 spi2_sin spi0_pcs5 fb_ad28 70 ptc0 / adc0_se14/ tsi0_ch13 / adc0_se14/ tsi0_ch13 ptc0 spi0_pcs4 pdb0_extr g i2s0_txd fb_ad14 pinout k60 sub-family data sheet data sheet, rev. 5, 5/2011. 70 preliminary freescale semiconductor, inc.
100 lqf p pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 71 ptc1 / adc0_se15/ tsi0_ch14 / adc0_se15/ tsi0_ch14 ptc1 spi0_pcs3 uart1_rts _b ftm0_ch0 fb_ad13 72 ptc2 / adc0_se4b/ cmp1_in0/ tsi0_ch15 / adc0_se4b/ cmp1_in0/ tsi0_ch15 ptc2 spi0_pcs2 uart1_cts _b ftm0_ch1 fb_ad12 73 ptc3 /cmp1_in1 /cmp1_in1 ptc3 spi0_pcs1 uart1_rx ftm0_ch2 fb_clkout 74 vss vss vss 75 vdd vdd vdd 76 ptc4 ptc4 spi0_pcs0 uart1_tx ftm0_ch3 fb_ad11 cmp1_out 77 ptc5 ptc5 spi0_sck lpt0_alt2 fb_ad10 cmp0_out 78 ptc6 /cmp0_in0 /cmp0_in0 ptc6 spi0_sout pdb0_extr g fb_ad9 79 ptc7 /cmp0_in1 /cmp0_in1 ptc7 spi0_sin fb_ad8 80 ptc8 / adc1_se4b/ cmp0_in2 / adc1_se4b/ cmp0_in2 ptc8 i2s0_mclk i2s0_clkin fb_ad7 81 ptc9 / adc1_se5b/ cmp0_in3 / adc1_se5b/ cmp0_in3 ptc9 i2s0_rx_bc lk fb_ad6 ftm2_flt0 82 ptc10 / adc1_se6b/ cmp0_in4 / adc1_se6b/ cmp0_in4 ptc10 i2c1_scl i2s0_rx_fs fb_ad5 83 ptc11 /adc1_se7b /adc1_se7b ptc11 i2c1_sda i2s0_rxd fb_rw_b 84 ptc12 ptc12 uart4_rts _b fb_ad27 85 ptc13 ptc13 uart4_cts _b fb_ad26 86 ptc14 ptc14 uart4_rx fb_ad25 87 ptc15 ptc15 uart4_tx fb_ad24 88 vss vss vss 89 vdd vdd vdd 90 ptc16 ptc16 can1_rx uart3_rx enet0_158 8_tmr0 fb_cs5_b/ fb_tsiz1/ fb_be23_16 _bls15_8_b 91 ptc17 ptc17 can1_tx uart3_tx enet0_158 8_tmr1 fb_cs4_b/ fb_tsiz0/ fb_be31_24 _bls7_0_b 92 ptc18 ptc18 uart3_rts _b enet0_158 8_tmr2 fb_tbst_b/ fb_cs2_b/ fb_be15_8_ bls23_16_b 93 ptd0 ptd0 spi0_pcs0 uart2_rts _b fb_ale/ fb_cs1_b/ fb_ts_b pinout k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 71
100 lqf p pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 94 ptd1 /adc0_se5b /adc0_se5b ptd1 spi0_sck uart2_cts _b fb_cs0_b 95 ptd2 ptd2 spi0_sout uart2_rx fb_ad4 96 ptd3 ptd3 spi0_sin uart2_tx fb_ad3 97 ptd4 ptd4 spi0_pcs1 uart0_rts _b ftm0_ch4 fb_ad2 ewm_in 98 ptd5 /adc0_se6b /adc0_se6b ptd5 spi0_pcs2 uart0_cts _b ftm0_ch5 fb_ad1 ewm_out_ b 99 ptd6 /adc0_se7b /adc0_se7b ptd6 spi0_pcs3 uart0_rx ftm0_ch6 fb_ad0 ftm0_flt0 100 ptd7 ptd7 cmt_iro uart0_tx ftm0_ch7 ftm0_flt1 8.2 k60 pinouts the below figure shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. pinout k60 sub-family data sheet data sheet, rev. 5, 5/2011. 72 preliminary freescale semiconductor, inc.
60 59 58 57 56 55 54 53 52 51 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 pga1_dp/adc1_dp0/adc0_dp3 pga0_dm/adc0_dm0/adc1_dm3 pga0_dp/adc0_dp0/adc1_dp3 adc1_dm1 adc1_dp1 adc0_dm1 adc0_dp1 vregin vout33 usb0_dm usb0_dp vss vdd pte6 pte5 pte4 pte3 pte2 pte1 pte0 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vdd vss ptc3 ptc2 ptc1 ptc0 ptb23 ptb22 ptb21 ptb20 ptb19 ptb18 ptb17 ptb16 vdd vss ptb11 ptb10 ptb9 ptb3 ptb2 ptb1 ptb0 reset_b pta19 25 24 23 22 21 vssa vrefl vrefh vdda pga1_dm/adc1_dm0/adc0_dm3 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 ptd6 ptc7 ptc6 ptc5 ptc4 50 49 48 47 46 45 44 43 42 41 pta18 vss vdd pta17 pta16 pta15 pta14 pta13 pta12 vss vdd pta5 pta4 pta3 pta2 pta1 pta0 pte26 pte25 pte24 vbat extal32 xtal32 dac0_out/ cmp1_in3/adc0_se23 vref_out/cmp1_in5/ cmp0_in5/adc1_se18 98 ptd5 97 ptd4 96 ptd3 95 ptd2 94 ptd1 93 ptd0 92 ptc18 91 ptc17 90 ptc16 89 vdd 88 vss 80 ptc8 ptc9 ptc10 81 82 83 ptc11 84 ptc12 85 ptc13 86 ptc14 87 ptc15 100 ptd7 figure 31. k60 100 lqfp pinout diagram 9 revision history the following table provides a revision history for this document. table 50. revision history rev. no. date substantial changes 1 11/2010 initial public revision table continues on the next page... revision history k60 sub-family data sheet data sheet, rev. 5, 5/2011. freescale semiconductor, inc. preliminary 73
table 50. revision history (continued) rev. no. date substantial changes 2 3/2011 many updates throughout 3 3/2011 added sections that were inadvertently removed in previous revision 4 3/2011 reworded i ic footnote in "voltage and current operating requirements" table. added paragraph to "peripheral operating requirements and behaviors" section. added "jtag full voltage range electricals" table to the "jtag electricals" section. 5 6/2011 ? changed supported part numbers per new part number scheme ? changed dc injection current specs in "voltage and current operating requirements" table ? changed input leakage current and internal pullup/pulldown resistor specs in "voltage and current operating behaviors" table ? split low power stop mode current specs by temperature range in "power consumption operating behaviors" table ? changed typical i dd_vbat spec in "power consumption operating behaviors" table ? added enet and lptmr clock specs to "device clock specifications" table ? changed minimum external reset pulse width in "general switching specifications" table ? changed pll operating current in "mcg specifications" table ? added footnote to pll period jitter in "mcg specifications" table ? changed supply current in "oscillator dc electrical specifications" table ? changed crystal startup time in "oscillator frequency specifications" table ? changed operating voltage in "ezport switching specifications" table ? changed title of "flexbus switching specifications" table and added output valid and hold specs ? added "flexbus full range switching specifications" table ? changed adc asynchronous clock source specs in "16-bit adc characteristics" table ? changed gain spec in "16-bit adc with pga characteristics" table ? added typical input dc current to "16-bit adc with pga characteristics" table ? changed input offset voltage and enob notes field in "16-bit adc with pga characteristics" table ? changed analog comparator initialization delay in "comparator and 6-bit dac electrical specifications" ? changed code-to-code settling time, dac output voltage range low, and temperature coefficient offset voltage in "12-bit dac operating behaviors" table ? changed temperature drift and load regulation in "vref full-range operating behaviors" table ? changed regulator output voltage in "usb vreg electrical specifications" table ? changed i lim description and specs in "usb vreg electrical specifications" table ? changed dspi_sck cycle time specs in "dspi timing" tables ? changed dspi_ss specs in "slave mode dspi timing (low-speed mode)" table ? changed dspi_sck to dspi_sout valid spec in "slave mode dspi timing (high- speed mode)" table ? changed reference oscillator current source base current spec and added low- power current adder footer in "tsi electrical specifications" table revision history k60 sub-family data sheet data sheet, rev. 5, 5/2011. 74 preliminary freescale semiconductor, inc.
how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com document number: k60p100m100sf2 rev. 5, 5/2011 preliminary information in this document is provided solely to enable system and software implementers to use freescale semiconductors products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "typical" parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals", must be validated for each customer application by customer's technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claims alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as their non-rohs-complaint and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale's environmental products program, go to http://www.freescale.com/epp. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2010C2011 freescale semiconductor, inc.

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